Field of the Invention
The present invention relates to a semiconductor device, and in particular to a semiconductor device including signal lines connecting a region in which light receiving elements are formed with a peripheral region.
Description of the Background Art
As CMOS image sensors achieve higher performance, it becomes increasingly important to suppress variation in characteristics among elements constituting the same. For example, Japanese Patent Laying-Open No. 2007-180336 discloses a configuration suppressing variation in signal voltage among a plurality of light receiving elements in a region in which the light receiving elements are arranged.
Further, as CMOS image sensors are miniaturized, wiring layers become thinner, which may cause weakening of the function of shielding a region in which entrance of light is undesirable. This is because a thin film is more likely to transmit light than a thick film. For example, Japanese Patent Laying-Open No. 2010-135844 proposes a configuration achieving both a thinner wiring layer by downsizing light receiving elements of a CMOS (Complementary Metal Oxide Semiconductor) image sensor and ensured shielding property for a region in which entrance of light is undesirable.
When a semiconductor device including a CMOS image sensor is formed, polishing processing called CMP (Chemical Mechanical Polishing) is generally performed to planarize a surface of a formed insulating film or the like. During the CMP, a force is applied downward from above the surface of the formed thin film. In order to receive the force more uniformly, a columnar thin film layer may be formed as a so-called dummy in a region in which thin film layers are arranged in a relatively low planar density, of a region subjected to the CMP. This dummy will be hereinafter referred to as a CMP dummy.
A CMOS image sensor has a light receiving element region in which light receiving elements such as photodiodes are arranged, and a peripheral region for performing input/output of an electric signal between the light receiving element region and an external circuit. Between the light receiving element region and the peripheral region, there exists a region in which elements such as a transistor are not arranged (i.e., a boundary region between the light receiving element region and the peripheral region). In the boundary region, only signal lines performing input/output of electric signals between the light receiving elements and elements in the peripheral region are arranged.
However, it is preferable to arrange a CMP dummy particularly in the boundary region in order to improve processing accuracy of the CMP as described above. Since a CMP dummy is formed by automatically computing a region in which it is preferably arranged, a planar shape and arrangement thereof are random relative to arrangement of regular elements and wires. As a result, impedance mismatching has occurred among the plurality of signal lines arranged in the boundary region due to random arrangement of the arranged CMP dummy. As CMOS image sensors achieve higher performance, it becomes increasingly important to suppress impedance mismatching among elements constituting the same.
Although the patent documents described above consider variation in characteristics among elements and maintaining of shielding property, they do not consider variation in electrical characteristics due to a CMP dummy arranged in a region having a low density of elements, wiring layers, and the like, and they do not include a description about a CMP dummy at all. Therefore, these documents neither disclose nor suggest means for solving the above problem.